Semiconductor integrated circuit device

Abstract

Abstract PURPOSE:To eliminate leakage between the emitter and collector of a lateral transistor, by a method wherein an MOS gate is provided between the emitter region and the substrate collector region, and a potential to prevent in inversion of the base region under the gate is applied when the lateral transistor is in an inoperative state. CONSTITUTION:In order to improve driving capacity, a lateral N-P-N transistor T4 is provided in a CMOS gate circuit comprising, e.g., a PMOSFETT6 and an NMOST8. Between a substrate collector region 31 of the T4 and an emitter region 33 disposed adjacently thereto through a base region 32, a gate insulating film 35 and a gate electrode 36 provided in order to connect an MOSFETT5 with the transistor T4 in parallel. By connecting the gate electrode 36 of the T5 to an output terminal O2, the potential of the gate 36 is at ground level when the T4 is in an inoperative state with input terminals I3, I4 at VD level, thereby to make it possible to prevent an N type inversion layer from being induced in the base region. Thus, it is possible to improve the driving capacity of the CMOS circuit and lower the power consumption simultaneously therewith.

Inventors

• 👤 Hiroshi Enomoto
• 👤 Tsuneo Nakamura

Bibliographic Details