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JPS5772351A Expired / Lapsed JP ⏱️ 0.0 years remaining

Fabrication of wiring structure

Assignee: Hitachi Ltd
•
Filing: 1980-10-24
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Granted: —
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Expires: 2000-10-24
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Abstract

Abstract PURPOSE:To prevent the deterioration of passivation effect and increase of floating capacitance by a method wherein a contact hole forming area part is formed so that it is thiner than in other area and after an insulating layer of a fast-etching speed has been formed other insulating layers are formed. CONSTITUTION:Whole surface of a substrate 1 is covered by SiO2 layer P. Part of SiO2 layer 2 is mad thinner by etching, and unwanted SiO2 layer 2 in the circumference is etched away. Next, phosphor glass layer 3 and CVD SiO2 layer 4 are superimposed in turn on the upper surface of substrate 1. Then, insulating layers 4, 3 and 2 are partially etched away to form a contact hole 6. Afterward, a tungsten layer 9 is laid by spattering and etching. Subsequently, a metal layer 10 consisting of a titan layer and a palladium layer is formed on it, and then a bump electrode 11 is formed on the metal layer 10. Then, etching the backside of substrate 1, a gold layer 12 and a silver layer 13 in turn are superimposed on the backside of substrate 1 to form an electrode.

Inventors

  • 👤 Akihiro Sato
  • 👤 Heiji Moroshima

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 09:23
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/01; H10W72/012; H10W72/20; H10W72/251

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