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JPS5771587A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor storing device

Assignee: Toshiba Corp
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Filing: 1980-10-22
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Granted: —
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Expires: 2000-10-22
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Abstract

Abstract PURPOSE:To reduce an occupied area of a memory cell, by constituting it so as to connect plural double type MOSFETs in series. CONSTITUTION:A memory cell 16 consists of double gate type MOSFETs, and plural series circuits 17 are formed by connecting in series the same number of MOSFETs respectively. In case when a data is read out from this storing device, R/W and a signal A are set to ''1'' and ''0'', respectively, and while a clock signal phi is set to ''1'', a ''0'' signal and a ''1'' signal are supplied to a selective line wire and a non-selective line wire, respectively, from a line decoder 14, and a signal of a connecting point S in that case is detected. Subsequently, in case when a data is written to the cell 16, the signal R/W is set to ''0'', and while the signal phi is set to ''1'', high potential voltage V1 and voltage of lower potential the V1 are supplied to the selective line wire and the non-selective line wire, respectively, and the signal A is set to ''1'' in accordance with a write data. According to such a constitution, it is unnecessary to apply ground potential to the source of each cell 16, and also a contact hole for for connecting each drain and a row wire 13 is not required, therefore, an occupied area of the cell is reduced.

Inventors

  • 👤 Hiroshi Iwahashi
  • 👤 Masamichi Asano

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-23 18:33
CPC Classifications
G; G11; G11C; G11C7/00

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