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JPS5754409A Expired / Lapsed JP ⏱️ 0.0 years remaining

Signal interruption circuit

Assignee: Toshiba Corp
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Filing: 1980-09-18
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Granted: —
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Expires: 2000-09-18
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Abstract

Abstract PURPOSE: To obtain an signal interruption circuit suitable for circuit integration, by removing a DC cut capacitance, through the prevention of the production of pop sound at muting on/off. CONSTITUTION: Transistors Q 21 ∼Q 30 form differential pairs, circuits 21, 22, 23 constitute double balanced type differential amplifiers, a circuit 25 gives a bias and also a muting pulse P through a circuit 26. Currents flowing from the circuit 21 to 22 are taken as I 1 , I 2 and a current flowing to the circuit 24 is taken as I 3 , and selection is made as I 1 <I 3 <I 1 +I 2 ,and I 2 <I 3 < 1 +I 2 .Pulse are inputted through the circuit 26, and when an audio signal S is not muted, a signal is given to a common emitter of another differential pair to cut off this pair only, and when muting is desired, the signal is given to the common emitter of one differential pair to cut- off this pair only and at the inversion of on/off switching of muting, both differential pairs are made conductive at the same time. With this constitution, the output potential is not changed, no pop sound is outputted, and capacitance for DC cut-off is unnecessary and circuit integration is made easy since semiconductors and resistors and used. COPYRIGHT: (C)1982,JPO&Japio

Inventors

  • 👤 Hiroyasu Yamaguchi
  • 👤 Yasuhiro Kodera

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 16:48
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/34; H03G11/00; H03G11/08

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