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Patent JPS5748833A successfully refreshed from Google Patents.
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JPS5748833A Expired / Lapsed JP ⏱️ 0.0 years remaining

Gate circuit

Assignee: NEC Corp
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Filing: 1980-09-05
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Granted: —
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Expires: 2000-09-05
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Abstract

Abstract PURPOSE:To increase the margin of noise, by providing a depletion type MOSFET between the source and ground of an input device of an inverter circuit of the 1st E/D type and connecting the output of the 2nd inverter circuit to the gate. CONSTITUTION:When a voltage between the source and substrate of an input device Q5 is increased, the apparent threshold voltage of the input device Q5 is increased by the substrate effect. In the gate circuit, a potential difference between the source and the substrate of the input device Q5 is produced with the depletion type MOSFETQ6 to produce the substrate effect. Thus, when the input signal is at low level, the apparent threshold voltage of the input device Q5 is increased and the noise margin is made greater. Since the gate of the MOSFETQ6 is connected to the output OUT of the 2nd inverter circuit, the input signal is in phase with the output of the 2nd inverter circuit, and the mutual conductance of the FETQ6 is changed by the input voltage.

Inventors

  • 👤 Kazuyuki Miyadera

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 08:32
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K19/09443; H03K19/09445

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS522160A Cited
JPS5269545A Cited

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