Patent JPS5748830A successfully refreshed from Google Patents.
JPS5748830A
Expired / Lapsed
JP
⏱️ 0.0 years remaining
Power-on reset signal generating circuit
Assignee: Pioneer Corp
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Filing: 1980-09-08
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Granted: —
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Expires: 2000-09-08
Abstract
Abstract PURPOSE:To increase the delay time and to produce a sure power-on reset signal, by selecting that the ratio of channel length to width of FETs constituting inverters can be smaller than that constituting an external circuit. CONSTITUTION:The ratio, W/L, of channel width W to channel length L of each FET constituting a C-MOS inverter is made remarkably small and the output characteristics can be mitigated. Thus, the circuit power supply reaches already a specified level +VDD at t5 after the period T when the output of the final stage of FET45 rises, allowing sure reset.
Inventors
- 👤 Kunihiko Hirashima
Bibliographic Details
Application Number
—
Jurisdiction
JP
Data Source
google_patents
Last Synchronized
2026-10-30 07:56
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22
Claims Analysis
Total Claims: 0
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References Cited (Backward Citations)
JPS5099038A
Cited
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