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JPS5698781A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory device

Assignee: NEC Corp
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Filing: 1979-12-29
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Granted: —
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Expires: 1999-12-29
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Abstract

Abstract PURPOSE:To prevent the accumulation of errors of data read out in a rare case by readling all data out of memory cells within a definite time during refreshing operation, and by correcting and rewriting erroneous data in a memory if it is detected. CONSTITUTION:In refreshing operation, a refresh address generating circuit (composed of refresh counter 23 and refresh address register 24) generates cyclically a column address for selecting readout data bits and a chip selection address and, while reading all memory contents of memory part 21, detects 28 an error of the readout data; erroneous data is corrected 31 and the corrected data and a check bit are rewritten together in the address where the error occured. Therefore, even an error of data read out of an address read out in a rare case is corrected and the accumulation of errors is prevented.

Inventors

  • 👤 Yoshifumi Sasamoto

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 12:08
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1076; G06F11/1008

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS52127036A Cited
JPS52129334A Cited

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