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JPS5696328A Expired / Lapsed JP ⏱️ 0.0 years remaining

Logical arithmetic operating device

Assignee: Fujitsu Ltd
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Filing: 1979-12-28
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Granted: —
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Expires: 1999-12-28
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Abstract

Abstract PURPOSE: To obtain the operation result in a comparatively high speed, by combining a carry preserving adder and a carry propagating adder to obtain a simple logical arithmetic operating device. CONSTITUTION: The C input of carry preserving adder CSA having three input terminals is made all 0 or all 1, and two A and B inputs are used as operands, and their two outputs D and R are connected to input terminals E and F of carry propagating adder CPA. By making either of input terminals E and F all-zero signals, output of output terminals R and D appear as S as they pass through carry propagating adder CPA without stopping, thus obtaining a simple logical arithmetic operating device. COPYRIGHT: (C)1981,JPO&Japio

Inventors

  • 👤 Akio Shinagawa
  • 👤 Katsuyuki Iwata

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 09:08
CPC Classifications
—

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