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JPS5677985A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory device

Assignee: Toshiba Corp
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Filing: 1979-11-26
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Granted: —
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Expires: 1999-11-26
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Abstract

Abstract PURPOSE:To increase both reliability and data processing capacity, by reading the data of the specified address during a refresh cycle and then carrying out the detection and correction of an error of the read-out data. CONSTITUTION:The column address strobe (CRAS) signal or the chip selection signal is applied selectively to the specified block within the memory element blocks 1A1-1An and 1D1-1Dn during the refresh cycle. Then the data of the specified address is read out to be stored in the data register 2. This data is sent to the error detection/correction (ECC) circuit 3 in the refresh cycle for checking of the error. In case a correctable error (such as 1-bit error) is detected, the error bit is corrected and then written into the above-mentioned specified address as the rewriting data (DI0-DIn-1) during the refresh cycle.

Inventors

  • 👤 Ginzo Yamazaki

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 08:16
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1076; G06F11/1008

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