High speed frequency division circuit

Abstract

Abstract PURPOSE:To enable the frequency division of the >=100MHz high frequencies signal, by connecting the input and output terminals of the inverter circuit to each of two terminals of the transfer gate circuit. CONSTITUTION:When the potential at the input and output terminals A, B of the inverter circuit 12 is respectively at high and low level, and when the clock signal phi is at low level and the transfer gate circuit 11 is nonconductive, if the signal phi is changed to high level, the potential at the point A is changed to low level after the specified time delay, because of the conduction of the circuit 11. In this case, when the potential at the point B is at high level in a given time constant, the signal phi is already going to be low level, the circuit 11 is nonconductive and the signal at the point B can not be delivered to the point A. Accordingly, since the high level signal at the point B is not fed to the point A, frequency dividing operation, 1/2, can be made.

Inventors

• 👤 Hirohei Kawakami

Bibliographic Details