Synchronizing type logic circuit

Abstract

Abstract PURPOSE:To reduce the power consumption, by synchronizing the current required for the level shift transistor TR of the synchronizing bipolar logic circuit to the clock CK input. CONSTITUTION:When CKphi is input, the differential pair TR3, 4 of common emitter connection and TR1 are responded, and the load voltage corresponding to the data input D is appeared across the resistances 11, 12. During the period of CKphi, TR16, 17 of the current switching means are nonconductive and the data read in are not appeared at the emitter of the level shift TR7, 8. Next, when inversion phi enters, TR16, 17, 7, 8 are conductive and the data appears at the emitter of TR7, 8 and TR5, 6 are latched to output signals Q, Q'. In this case, TR1, 3, 4 are nonconductive and FF circuit is inactive to the change of the input data D. Since current flows to TR7, 8 only at the inversion phi, the power consumption per FF can remarkably be reduced.

Inventors

• 👤 Yasutaka Horiba
• 👤 Kenji Murakami

Bibliographic Details