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JPS566569A Expired / Lapsed JP ⏱️ 0.0 years remaining

Sampling method for facsimile signal

Assignee: Sanyo Electric Co Ltd
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Filing: 1979-06-28
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Granted: —
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Expires: 1999-06-28
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Abstract

Abstract PURPOSE:To reproduce a good picture which is free from the jitter effect, by selecting the two sets of auxiliary sampling clocks of different phases and then setting the varying point of the picture signal at the center of the sampling timing. CONSTITUTION:The picture signal sent from demodulator circuit 10 receives the binary coding through waveform shaping circuit 11 to be sent to sampling clock comparator circuit 2. Circuit 2 produces auxiliary sampling clocks S1 and S2 of different phases by 180 deg. via oscillator circuit 13 and the clock signal generating part and then sampling signals J and K from clocks S1 and S2 each. These clocks and signals are then supplied to AND circuits 22 and 23 along with the signal sent from varying point detecting part 24. Then picture signal d near the varying point is sampled, and detection signals L1 and L2 corresponding to signal d are sent to clock selection circuit 4. Here clock S is selected to set the varying point of the picture signal at the center to be applied to sampling circuit 31 along with signal d. The clock is then sampled at circuit 31 and by main sample clock Sr to be supplied to recording device 16 through interface circuit 15.

Inventors

  • 👤 Hideji Yanase
  • 👤 Koji Ueda
  • 👤 Mitsugi Ikeda

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-29 07:48
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/40

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Total Claims: 0
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