Electric power amplifying circuit

Abstract

Abstract PURPOSE:To suit a power amplifying circuit for integration while improving reliability by eliminating the simultaneous conduction of upper-and lower-stage output transistors by increasing a minimum operation output voltage above the collector- emitter saturation voltage of a post-stage transistor among lower-stage output transistors. CONSTITUTION:When collector-emitter saturation voltage VCE(sat) of single-ended push-pull SEPP output lower-stage output transistor Q6 is nearly twice its base- emitter voltage VBE, collector-emitter voltage VCE of transistor Q6 never drops below 2VBE+VCE(sat) and transistor Q6 will not get saturated. On the other hand, when VCE(sat) of transistor Q6 is approximate three times its base-emitter voltage, VCE of transistor Q6 never drops below 3VBE+VCE(sat), so that transistor Q6 can be left unsaturated. Then, transistor Q6 can be used in the unsaturated state, so that transistors Q3 and Q6 can be prevented from turning on simultaneously.

Inventors

• 👤 Hisashi Katafuchi

Bibliographic Details