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JPS5651853A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Toshiba Corp
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Filing: 1979-10-04
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Granted: —
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Expires: 1999-10-04
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Abstract

Abstract PURPOSE:To obtain a high-integration resistor-on FET, by providing a high-resistance poly Si layer in an insulation gate-type FET through an insulation film and using an FET-contained current passage and a poly Si layer as a current passage of a separate system. CONSTITUTION:Four blocks of a memory cell are arranged symmetrically to the center point C. Poly Si insulation gate-type FETQ1-Q16 are prepared in the blocks. Large-capacity drivers Q1, Q2 and Q5, Q6..., which constitute an FF circuit, are arranged to face each other in a hatchetlike configuration so that an occupancy area can be reduced. Q3, Q4... for switching use are to be of small type and small capacity, and dispersion capacities of all FETs are to be made extremely small. A high- resistance section is partly provided by covering with the second poly Si layer, a separate-system current passage is provided on the driver, load resistance R1 of Q2 is arranged on Q1, and R1 is arranged on Q2. Others are processed in the same manner. For this reason, the FF conducts stable operation. Data lines D, grounding lines VSS, word lines W and power source lines VDD are all manufactured at the same time by the second poly Si layer. It is possible, by using this constitution, to form a static RAM of small occupancy area.

Inventors

  • 👤 Shoji Ariizumi
  • 👤 Makoto Segawa

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 22:35
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/021; H10B; H10B10/00; H10B10/15; H10W10/20

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS53148398A Cited

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