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JPS5651678A Expired / Lapsed JP ⏱️ 0.0 years remaining

Testing method for memory element and pattern generator for test

Assignee: NTT Inc
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Filing: 1979-10-03
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Granted: —
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Expires: 1999-10-03
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Abstract

Abstract PURPOSE: To make it possible to detect many faults of memory elements and selection mechanism simultaneously at a low access frequency by dividing a memory area into two groups according to the parity of the number of "1"s in address information and by making tests by writing data different between both groups. CONSTITUTION: The memory area of the memory element is divided into group A for address information containing an even number of bits "1" and group B for that containing an odd number of bits "1". Then, "1"(or "0") is written in one group on the whole to take a read and collation of the whole memory area and after "0"(or "1") is written in the other whole group, "1"(or "0") is written in the former group on the whole to perform a read and collation of the whole memory area. COPYRIGHT: (C)1981,JPO&Japio

Inventors

  • 👤 Tsutomu Ishikawa
  • 👤 Kazumitsu Matsuzawa
  • 👤 Noboru Onishi

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 15:49
CPC Classifications
—

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