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JPS5629757A Expired / Lapsed JP ⏱️ 0.0 years remaining

Analyzer for logic function working

Assignee: NEC Corp
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Filing: 1979-08-20
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Granted: —
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Expires: 1999-08-20
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Abstract

Abstract PURPOSE: To obtain the optimum design information of the subject unit for the logic function working analyzer which performs the monitor, diagnosis and working analysis each of a digital electronic computer, by having a dynamic execution for the logic of the subject unit with a proper monitor and diagnosis given to the subject unit. CONSTITUTION: The main memory device 3 extracts and then stores the status of a number of logic circuit terminals in the subject digital electronic computer 1 and via the interface control part 2. The time control part 4 connected to the part 2 illustrates the time of the computer 1, and the state of the logic circuit at the time specified through the part 4 is sent to the arithmetic collating circuit 5 for an arithmetic collation with reception of the take-in bit pattern of the device 3. The result of the arithmetic collation is sent to the matrix information control part 6, and the input information is edited at the part 6. And the output of the part 6 is supplied to the device 3 to be stored, and at the same time the contents of storage is utilized when necessary. As a result, a proper monitor and diagnosis are carried out for computer 1, thus obtaining the optimum design information of the subject unit. COPYRIGHT: (C)1981,JPO&Japio

Inventors

  • 👤 Takao Ichiko

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 22:33
CPC Classifications
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