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JPS5627952A Expired / Lapsed JP ⏱️ 0.0 years remaining

Circuit for generating substrate bias voltage

Assignee: Hitachi Ltd
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Filing: 1979-08-17
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Granted: —
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Expires: 1999-08-17
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Abstract

Abstract PURPOSE: To prevent the decrease in the operation speed and the erroneous operation of an IC circuit by eliminating the variation in a bias voltage in a semiconductor substrate due to the variation in a power supply voltage. CONSTITUTION: An oscillator ciruit 1 is constituted by a ring oscillator wherein an odd number of inverters IV 1 ∼IV 5 are cascaded and the output from the final stage inverter IV 5 is fedback to the first stage inverter IV 1 . a rectifier circuit 2 is constituted by: a capacitor C 1 whcih is connected between an output line L 1 and A line L 2 ; an enhancement-mode MISFET Q 1 , wherein the gate and the drain are connected to the line L 2 and the source is connected to the grouning point GND of the circuit; an enhancement-mode MISFET Q 2 , wherein the source is connected to the line L 2 and the gate and the drain are connected to the line VBB; and a resistor R 1 with the relatively high resistance value, which is connected between the line VBB and the grounding point GND. COPYRIGHT: (C)1981,JPO&Japio

Inventors

  • 👤 Noburo Tanimura
  • 👤 Kotaro Nishimura
  • 👤 Norimasa Yasui

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 16:25
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G11C5/00; G11C5/14; G11C5/145; G11C5/146

Claims Analysis

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References Cited (Backward Citations)

JPS54148492A Cited

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