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JPS562625A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of epitaxial wafer

Assignee: Shindengen Electric Manufacturing Co Ltd
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Filing: 1979-06-20
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Granted: —
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Expires: 1999-06-20
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Abstract

Abstract PURPOSE:To increase the current treating capacity of an epitaxial wafer per unit area without increasing the forward voltage drop by etching anisotropically the plane (100) of an Si substrate to form ruggedness thereon and accumulating an epitaxial layer thereon. CONSTITUTION:The pattern of SiO2 film 4 is formed on the N-type Si substrate 1 having a plane (100), and is aniostropically etched. Then, an Si layer 2 containing no addition is accumulated on the surface opposite to the surface formed with ruggedness, and an N-type Si layer 3 is epitaxially formed on the rugged surface. The angle Q of the ruggedness thus becomes approx. 55 deg. to increase the area 1.72 times as large as the flat plate. The area of the rugged surface may be increased 2.366 times as large as the original area under the control of the shape (sizes a, b and h) of the ruggedness. A Schottky barrier metal 5 such as Cr or the like is attached to the layer 3. In this structure the area of the substrate can be reduced in the same current treating capacity without increasing the forward voltage drop. Accordingly, it is effective to be applied to a diode having less implantation and to Schottky barrier diode.

Inventors

  • 👤 Yuki Shimada
  • 👤 Shohei Sekiya
  • 👤 Katsunori Ichikawa

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 16:26
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/24; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411

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