Bit line control circuit

Abstract

Abstract PURPOSE: To shorten the read time of a semiconductor memory that uses I 2 L memory cells, by setting a bit line clamp level higher in read operation than in write operation. CONSTITUTION: Clamp level change over circuit EX consisting of transistor Tr Q 11 and Q 12 is provided and with its output. clamp level Vc of the memory consisting of I 2 L memory cells MC 1 and MC 2 is changed over. Namely, write-enable inverted signal WE' is held at level L in write operation and TrQ 12 turns on to flow electric current Ic to resistance Rc, thereby decreasing level Vc to the low level. In read operation, on the other hand, signal WE' is held at level H and TrQ 11 turns on, so that level Vc rises to high level V co . Thus, level Vc is made higher in read operation than in write operation so as to shorten the time when the potential difference between bit lines B 0 and B 1 increases from the cross point between potentials of word lines W 1 + and W 2 + up to a fixed value, so that the read time can be shortened. COPYRIGHT: (C)1981,JPO&Japio

Inventors

• 👤 Kazuhiro Toyoda

Bibliographic Details