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JPS5614744A Expired / Lapsed JP ⏱️ 0.0 years remaining

Bus check system

Assignee: Fujitsu Ltd
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Filing: 1979-07-17
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Granted: —
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Expires: 1999-07-17
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Abstract

Abstract PURPOSE:To detect securely a fault of a data bus and also to detect the faulty bus concretely by checking whether the bus is in normal operation even when communication data of the bus are asynchronous mutually. CONSTITUTION:Inputs from transmission-side buses L0, L1 and L2 are supplied to multiplexer 1, the output of which is sent to counter 2. Inputs from reception- side buses L0', L1' and L2', on the other hand, are input to multiplexer 5, whose output is supplied to counter 6. The output of transmission-side counter 2 passes through AND circuit 3 to obtain signal A for control over counter 9, and the output of reception-side counter 6 changes into signal B by passing through AND circuit 7 to control counter 10. Therefore, even when communication data of the bus by counters 9 and 10 are asynchronous mutually, a check on whether the bus is in normal operation can be made, so that a fault of the data bus and the faulty bus can be detected securely and concretely.

Inventors

  • 👤 Takahiro Sakuraba

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 22:24
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/40; G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4022

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