System clock generating circuit in integrated circuit

Abstract

Abstract PURPOSE:To reduce power consumption of the system clock SCK generating circuit, by controlling generation and stopping of basic CK by the control signal from the static (CK) control (CT) signal generating circuit. CONSTITUTION:Basic CK generating circuit H stops the operation by control signal ST generated by the CKCT signal generating circuit consisting of D type FFs 3 and 6, RS FFs 4 and 5, OR gates, inverters and AND gates, and signals A', A, B' and B derived from inverters I1-I4 are held in states 1, 0, 1 and 0, and power is not consumed. When the reset input of FF5 is 0, control signal SL becomes 1 and is given to OR gates 21-25 of the SCK generating circuit, and SCKs phi1-phi5 are held in state 1, and power consumption is reduced. When the system is in the holding state, signals ST and SL are generated by an instruction to stop SCK for circuits other than minimum circuits, and the CKCT signal generating circuit is constituted with a static logical operation circuit, thus power consumption is reduced.

Inventors

• 👤 Yoshikazu Nishiura
• 👤 Takiji Mineyama
• 👤 Kazuo Inoue

Bibliographic Details