Patent JPS56129374A successfully refreshed from Google Patents.
← Back to Patent Explorer
JPS56129374A Expired / Lapsed JP ⏱️ 0.0 years remaining

Writing and cancelling methods of fixed memory

Assignee: Fujitsu Ltd
•
Filing: 1980-02-22
•
Granted: —
•
Expires: 2000-02-22
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To enable a voltage to be made low, to reduce a power source terminals number of MOS chip and to easily write and cancel by enabling a carrier to be injected to a floating gate at a drain voltage of less than an avalanche voltage. CONSTITUTION:A sources and a drain D are formed on a silicon semiconductor substrate SUB, and the floating gate FG is formed on the substrate SUB between the source S and the drain D through a silicon oxidized film OX1. A control gate CG of Al or the like is formed on the top of the gate FG through the silicon oxidized film OX2. The substrate SUB is earthed, a positive voltage V0 reverse-biasing a junction between the drain D and the substrate SUB is applied to the drain D of a memory cell to make the avalanche fall occur between the drain D and the substrate SUB at writing. On the other hand, at cancelling, the avalanche is fallen, a negative voltage VG being applied to the gate CG, enabling the voltage to be made low and the writing and cancelling to easily be made.

Inventors

  • 👤 Hideki Arakawa

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 04:54
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/686

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag