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JPS56129341A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integrated circuit device

Assignee: Hitachi Ltd
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Filing: 1980-03-14
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Granted: —
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Expires: 2000-03-14
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Abstract

Abstract PURPOSE:To improve the mounting density by a device wherein a plurality of blocks arranged on a semiconductor chip in the form of almost matrix are formed to have smaller size at the center of the chip and to have gradually increased size toward the peripheral portion thereof. CONSTITUTION:The blocks 2 arranged on a semiconductor chip 1 in the form of almost matrix are formed to have gradually increased size toward the peripheral portion thereof; namely a1<a2<a3 and b1<b2<b3. An interblock wiring region 8 is provided between the respective blocks. The relation that a1=b1, a2=b2 and a3=b3 is also satisfied. Wirings formed in a wiring region 7 within each block and the wiring region 8 between the blocks have a multilayer structure. With this arrangement, an area of the wiring region between blocks becomes larger at the center with high wiring density and smaller at the peripheral portion with low wiring density, thus resulting in the increased mounting density.

Inventors

  • 👤 Hidekazu Minami
  • 👤 Masao Kato
  • 👤 Tsutomu Sumimoto

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 03:26
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/10

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