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Patent JPS56118366A successfully refreshed from Google Patents.
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JPS56118366A Expired / Lapsed JP ⏱️ 0.0 years remaining

Preparation of semiconductor device

Assignee: Hitachi Ltd
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Filing: 1980-02-22
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Granted: —
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Expires: 2000-02-22
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Abstract

Abstract PURPOSE:To form in a self-alignment mode channel stoppers corresponding respectively to each well of P and N, by making use of the difference in the thickness of the oxidized films. CONSTITUTION:On an SiO2 film 11 on an N<--> Si substrate 10, an Si3N4 mask is formed, and after As ions implantation a selective oxidization is performed, an SiO2 film 14 and N<+> well 13 are formed. After removing the mask B ions are implanted and a P<-> well 15 is formed by heat treatment in N2. After B ions implantation and oxidation a P<--> type 17 and N<--> type 19 channel stoppers are formed by means of an Si3N4 mask 16. The SiO2 film on the layers 13, 15 is removed and a gate oxidized films 20, 21a and a P dope polycrystalline Si electrode 22, 23 are formed, which are covered by an SiO2 film and an Si3N4 film 25 is stacked. Thereafter successive ions implantations are performed by means of the SiO2 mask and P<+> layers 40, 41 and N<+> layers 42, 13 are selectively formed. A protective film of PSG28 is formed and electrodes 29-32 are mounted. With such an arrangement, the process is simplified without mask alignment and because the space for mask is spared a CMOSIC of high integration can be obtained.

Inventors

  • 👤 Koichi Nagasawa
  • 👤 Satoshi Meguro

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-30 23:42
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/02; H10D84/03; H10D84/038

Claims Analysis

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References Cited (Backward Citations)

JPS5661139A Cited

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