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JPS5611699A Expired / Lapsed JP ⏱️ 0.0 years remaining

Parity check system

Assignee: Toshiba Corp
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Filing: 1979-07-09
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Granted: —
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Expires: 1999-07-09
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Abstract

Abstract PURPOSE: To obtain the parity check system in which effective use of memories can be made, by reading out the parity bit based on the address from parity bit ROM for parity check. CONSTITUTION: When ROM1 1 is selected with CPU, the address signal is fed also to the parity bit ROM3, the parity bit corresponded is read out and fed to the parity check circuit 7 via the AND circuits 5 1 ..., OR circuit 6 open through the selector 4 to which the selection signal is fed. Further, the parity check for the data bit read out from ROM1 1 is made. With this constitution, the same capacity as the data capacity can not necessarily be assigned to each ROM1 1 ... for the parity bit use, allowing to effectively use the memory. COPYRIGHT: (C)1981,JPO&Japio

Inventors

  • 👤 Hajime Harada
  • 👤 Yasuji Hatakeyama

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 05:07
CPC Classifications
—

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