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JPS5583333A Expired / Lapsed JP ⏱️ 0.0 years remaining

D-type latch circuit

Assignee: Advantest Corp
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Filing: 1978-12-20
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Granted: —
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Expires: 1998-12-20
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Abstract

Abstract PURPOSE:To make it possible to obtain invariably-constant set-up time without reference to a previous state, by connecting the common current path of FF to the other output side of a current change-over switch. CONSTITUTION:Once a clock pulse is supplied to terminal 16, transistor Tr12 conducts to activate differential type comparator circuit 18. When the data of input terminal 23 is higher than the comparison voltage of terminal 24, Tr21 and Tr22 are ON and OFF respectively, and output terminals 36 and 37 are held at high and low level respectively. On the other hand, since Tr13 is OFF, Trs 28 and 29 are both OFF and a state bearing no relation to the latch state of previous data is set. After a clock pulse falls, Tr13 conducts with a little bit delay and Tr12 gets cut off, so that a common emitter current of Tr21 and Tr22 will be switched to that of Tr28 and Tr29. For example, if Tr21 is ON, Tr28 gets cut off and even when Tr22 is OFF, Tr29 also gets cut off. In this way, the data of terminal 23 is latched by FF25.

Inventors

  • 👤 Toshiaki Wakita

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-28 22:53
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885

Claims Analysis

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References Cited (Backward Citations)

JPS5145974U Cited

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