Master slice semiconductor integrated circuit

Abstract

Abstract PURPOSE: To reduce the electrostatic capacity of polycrystalline silicon lines crossed with power lines and obtain a master slice integrated circuit which can rapidly operate a logical circuit, by embedding the polycrystalline silicon lines between rows of cells. CONSTITUTION: Driving MOS transistors of a master slice integrated circuit are independent of one another as to respective cells. Polycrystalline silicon lines H 1 -H 2 , H 3 -H 4 , H 5 -H 6 are provided between cells across power lines VDD, VSS to perform longitudinal wiring on regions between the rows of the cells. When the longitudinal wiring is effected on a chip, the longitudinal polycrystalline silicon line H 1 -A 1 -H 2 , H 3 -A 3 -H 4 or H 5 -A 5 -H 6 is used. The silicon line is not crossed with any driving transistors. As a result, rapid operation can be performed because the loaded electrostatic capacity of the polycrystalline silicon lines laid on a field region of large oxide film thickness is small. COPYRIGHT: (C)1980,JPO&Japio

Inventors

• 👤 Takeo Tanaka
• 👤 Masahiko Nakajima

Bibliographic Details