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JPS558160A Expired / Lapsed JP ⏱️ 0.0 years remaining

Oscillation circuit

Assignee: Seiko Epson Corp
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Filing: 1978-07-04
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Granted: —
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Expires: 1998-07-04
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Abstract

Abstract PURPOSE: To obtain an oscillation circuit featuring a small amount of power consumption and low oscillation start voltage by using such circuit that features the effect equivalent to that obtained by increasing the resistance of the inverter comprising IGFET and the resistance. CONSTITUTION: The power consumption is reduced since bias circuit C consisting of complementarily connected IGFET, main oscillation circuit A and output amplifier circuit B operate each near the threshold level. And the large amplified oscillation AC waveform is piled onto about 1/2 DC bias level of the power voltage and delivered to output out of circuit B. But output terminal out becomes the gate input of complementarily connected IGFET, and thus a perfect matching is secured for the logic level to the complimentary circuit. Furthermore, the current bias is constant for all circuits of C, A and B each since the output of circuit C is constant to the power voltage. As a result, the uniform oscillation characteristics can be obtained regardless of the level of the power voltage, thus obtaining an oscillation circuit featuring the low oscillation start voltage and reduced power consumption. COPYRIGHT: (C)1980,JPO&Japio

Inventors

  • 👤 Tatsuji Asakawa
  • 👤 Shinji Morozumi

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 17:14
CPC Classifications
—

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