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JPS5575253A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: CHIYOU LSI GIJUTSU KENKYU KUMIAI
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Filing: 1978-12-04
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Granted: —
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Expires: 1998-12-04
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Abstract

Abstract PURPOSE:To stabilize and integrate the performance of a MOS random access memory (RAM) by providing a layer for recoupling minority carriers in a semiconductor substrate. CONSTITUTION:B Ion is implanted onto a semiconductor substrate 1 to thereby form a p<+>-type layer 11. Then, a field effect transistor (FET) is formed by a substrate, diffused layers 2, an oxide film 5 and a gate electrode 6, a capacitor is formed by a gate electrode 7, an oxide film 5 and an inversion layer 8, and a dynamic random access memory (RAM) is formed by connecting the transistor and the capacitor in series. According to this configuration, excessive electrons are drifted and when they enters the p-type layer 11, they are recoupled to be vanished. Accordingly, when the excessive electrons entered into the substrate 1 by the impact ionization current and the forward current of the pn-junction move to the surface, they are recoupled upon passage of the layer 11 to largely reduce the amount of the electrons to reach the inversion layer 8. Thus, the positive charge stored between the electrode 7 and the inversion layer 8 is retained for long time. The electrons generated on the surface of the substrate 1 are recoupled upon passage of the layer 11. As a result, the integration of the semiconductor device can be readily realized.

Inventors

  • 👤 Makoto Taniguchi

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 12:36
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30

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