Information receiving unit

Abstract

Abstract PURPOSE: To facilitate the high-speed receiving display operation of a TV character multiple broadcast by providing a write processing circuit, a main memory, a read processing circuit and a micro processor unit MPU and driving the MPU with two- phase clocks. CONSTITUTION: Received serial signals are converted to parallel signals byte by byte by write processing circuit 3 and are supplied to a data bus. MPU 4 fetches information signals from the data bus and writes pattern signals from the data bus to main memory 7 through address control circuit 6. MPU 4 is driven by two-phase clocks ϕ 1 and ϕ 2 from clock control circuit 10 and is provided with a data port which becomes high-impedance during a clock period dependent upon one clocks and reads out pattern signals from memory 7 to read processing circuit 8 through the data bus during this period. Circuit 8 converts parallel pattern signals to serial signals and sends them to display circuit 9. As a result, a high-speed processing can be performed without influence on data signal fetch in MPU 4. COPYRIGHT: (C)1980,JPO&Japio

Inventors

• 👤 Masayoshi Hirashima
• 👤 Hirosuke Okano
• 👤 Yukio Takada
• 👤 Hiroaki Saeki

Bibliographic Details