Negative resistance device

Abstract

Abstract PURPOSE: To reduce operating currents by utilizing substrate biasing effect that is obtanied through a source-to-source connection as well as a gate-to-gate connection of respective dual channel MOS transistors of N and P and also an interconnection between the drain of one transistor and the substrate of the other transistor. CONSTITUTION: The device is composed of dual channel MOS transistors Q 1 and Q 2 of N and P having a shallow drain region D, and a source region S and a gate electrode G of one tsansistor is coupled to those of the other transistor, respectively. In addition, the drain region D of one of them is connected to the substrate of the other, and the drain regions D of the transistors Q 1 and Q 2 are connected to an input terminal K and an earthed output point A, respectively. In these configuration, both the Q 1 and Q 2 will be conducted when the potential at P is low, and then returned to its non-conductive state due to substrate bias effected when the potential becomes high. Therefore, the device can operate with a small current of the order ranging from mA. to μA. COPYRIGHT: (C)1980,JPO&Japio

Inventors

• 👤 Tetsuya Iizuka

Bibliographic Details