Semiconductor integrated circuit device

Abstract

Abstract PURPOSE: To make easy the wiring, by using the fundamental element collecting region not in use to the wiring region, in the fundamental element collection having a small area of common parts with a simple construction for use with CMISFET. CONSTITUTION: On the P layer on the N type substrate, the gate terminals 1,2,N + layers 3 to 5, and P + layers 6 to 8 are formed with polycrystal Si, and they are constituted with every two P and N channel FET. The same channel commonly uses source or drain and different channels use gates commonly. Several hundred of the fundamental collective cells 21 are located via the transversal wiring region 23 longitudinally. The arrangement 20 is arranged via the logitudinal wiring region 22 and some 30 wiring are provided on the vacant region 22. Thus, the wiring rate can be increased, and the gate terminal is led out to the region 22 is symmetrical with left and right, causing easy wiring. Further, with suitable connections only between fundamental cells, many types of logic gate FET's can be formed. COPYRIGHT: (C)1979,JPO&Japio

Inventors

• 👤 Nobutake Matsumura
• 👤 Ryusuke Hoshikawa
• 👤 Yoshihide Sugiura
• 👤 Hiroaki Ichikawa
• 👤 Shoji Sato

Bibliographic Details