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JPS5458378A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device and its usage

Assignee: National Institute of Advanced Industrial Science and Technology
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Filing: 1977-10-19
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Granted: —
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Expires: 1997-10-19
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Abstract

Abstract PURPOSE: To establish the device having high speed switching and oscillating action, by enabling the circuit integration through the organic combination of FET and tunnel diode. CONSTITUTION: On the p type substrate 1, the shrinked n + soarce layer 2, drain layer 3, and shrinked r + layer 4 are placed, forming the tunnel junction 8 between the layers 3, 4, and 2. Next, the V groove is etched and the gate electrode 6 is made on the surface via the insulation film 5. To the layers 2 and 3, the electrodes S.D in contact with the layer 7 and the tunnel junction operation bias electrodes B1 and B2 are made to the layer 4. The junction 8 shows dynatron type negative resistance due to tunnel effect. When the bias of the layer 4 is fixed to a, the channel resistance of FET considering as load is changed with the voltage applied to the gate 6, and as the channel approaches ON, the load line is risen and the output is picked up as the voltage e, f opposed to the condition cd from the layer 3. In this case, the switching is not required for power application to the channel because of the tunnel effect, then very high speed switching can be made COPYRIGHT: (C)1979,JPO&Japio

Inventors

  • 👤 Hidekazu Suzuki
  • 👤 Yutaka Hayashi
  • 👤 Kiyoko Nagai

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 10:17
CPC Classifications
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