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JPS5457871A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Hitachi Ltd
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Filing: 1977-10-17
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Granted: —
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Expires: 1997-10-17
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Abstract

Abstract PURPOSE: To prevent the generation of a negative resistance due to a multiplication phenomenon is a high electrical field by inserting a P-type high-density layer into a MOS-type field effect transistor. CONSTITUTION: Onto n-type resist substrate 1, n-type layer 2 containing impurity phosphorus is formed and impurity boron is diffused to form P region 3. At the same time, P-type high density region 10 is also formed. Then n-type region 4 is diffusion-formed through an ordinary planar process. Next some part of heat-oxidized film 8 is removed to form V-shaped groove 11 and heat-oxidized film 5 is formed sequentially, on which Al gate electrode 6 and a source electrode are formed at the same time COPYRIGHT: (C)1979,JPO&Japio

Inventors

  • 👤 Takeaki Okabe
  • 👤 Isao Yoshida
  • 👤 Shikayuki Ochi
  • 👤 Minoru Nagata

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-27 20:14
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/668; H10D62/00; H10D62/10; H10D62/17; H10D62/393

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