Patent JPS5314564A successfully refreshed from Google Patents.
JPS5314564A
Expired / Lapsed
JP
⏱️ 0.0 years remaining
Bonding method of s# chip and substrate
Assignee: Hitachi Ltd
•
Filing: 1976-07-26
•
Granted: —
•
Expires: 1996-07-26
Abstract
Abstract PURPOSE: To reduce the temperature rise during operating by providing dummy terminals on the insulation layer of a Si substrate surface thereby increasing the reliability of strength resistance and temperature resistance cycles and providing a cooling plate on the rear of the substrate and connecting said plate to the dummy terminals. COPYRIGHT: (C)1978,JPO&Japio
Inventors
- 👤 Tasao Soga
- 👤 Tomiro Yasuda
- 👤 Kazuya Takahashi
- 👤 Kozo Odawara
Bibliographic Details
Application Number
—
Jurisdiction
JP
Data Source
google_patents
Last Synchronized
2026-11-03 16:58
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/071; H10W72/072; H10W72/20; H10W72/241
Claims Analysis
Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.