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JPH09321104A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integrated circuit

Assignee: NEC Yamagata Ltd
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Filing: 1996-05-30
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Granted: —
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Expires: 2016-05-30
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Abstract

Abstract Translated from Japanese (57)【要約】 【課題】TEGパターン領域を必要とする為、集積度が 向上しない。 【解決手段】ボンディング用パッド1を内部配線2に接 続する面積の大きい主パッド1Aと、この主パッド1A と電気的に分離された副パッド1Bとから構成し、テス ト用トランジスタ10Aをボンディング用パッドの下部 に形成し、その入出力部を主パッド1A又は副パッド1 Bに接続する。 (57) Abstract: A TEG pattern region is required, and therefore the degree of integration is not improved. SOLUTION: A main pad 1A having a large area for connecting a bonding pad 1 to an internal wiring 2, and the main pad 1A. And a sub-pad 1B electrically separated from each other, a test transistor 10A is formed below the bonding pad, and its input / output portion is the main pad 1A or the sub-pad 1B. Connect to B.

Inventors

  • 👤 Itaru Inoue
  • 👤 格 井上

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 21:40
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/27; H10P74/277

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