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Nonvolatile semiconductor storage

Assignee: Fujitsu Ltd
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Filing: 1993-03-17
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Granted: —
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Expires: 2013-03-17
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Abstract

Abstract Translated from Japanese (57)【要約】 【目的】 本発明は過剰消去対策のためソース選択トラ ンジスタを設けた不揮発性半導体記憶装置に関し、その 小型化及び低コスト化を図ることを目的とする。 【構成】 格子状に配置された複数の第一行線2A、2 B、…及び複数の第一列線3A、3B、…と、複数の第 二行線4A、4B、…と、制御電極が第一行線に接続さ れ第一電極が第二行線に接続され第二電極が第一列線に 接続された複数の不揮発性記憶素子1AA、1AB、… とを備える不揮発性半導体記憶装置において、第一列線 に平行に配置された一本又は複数本の第二列線5と、第 二列線5と第一行線の交点に対応して配置された複数の 能動素子6A、6B、…とを備え、読出時には選択した 素子の第二電極に第一電極より高い電圧を、書込時には 第一電極に第二電極より高い電圧を、消去時には第二電 極に第一電極より高い電圧印加するように構成する。 (57) [Summary] [Object] An object of the present invention is to reduce the size and cost of a nonvolatile semiconductor memory device provided with a source selection transistor as a measure against excessive erasure. [Structure] A plurality of first row lines 2A, 2 arranged in a grid pattern , And a plurality of first column lines 3A, 3B, ..., A plurality of second row lines 4A, 4B, ..., A control electrode is connected to the first row line, and a first electrode is connected to the second row line. The plurality of nonvolatile memory elements 1AA, 1AB, ... A non-volatile semiconductor memory device including: one or a plurality of second column lines 5 arranged in parallel to a first column line; and a second column line 5 and a first row line. , A plurality of active elements 6A, 6B, ... It is configured such that a voltage higher than that of the first electrode is applied to the second electrode.

Inventors

  • 👤 Tetsuji Takeguchi
  • 👤 哲治 竹口

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 18:13
CPC Classifications
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