Semiconductor non-volatile memory device

Abstract

Abstract Translated from Japanese (57)【要約】 （修正有） 【目的】６Ｖ程度の低電圧で情報を書込んでも正確に読 取りができ、長期間信頼性を維持できるメモリ窓幅の大 きく電荷保持性能が優れたトラップ型不揮発性半導体記 憶装置を提供する。 【構成】ｐ型Si基板３内にｎ + ドレイン26とｎ + ソース28 の形成によりチャンネル領域30が形成される。その上面 にSiO 2 薄膜５、次に多層積層絶縁膜22、さらにその上面 にポリSi膜24が形成される。多層積層絶縁膜22はSiN膜 層18、SiO 2 膜層20の順に交互に各３層積層した構造であ る。ポリSi膜24とチャンネル領域30間に電界を印加時、 チャンネル領域内の電子がSiO 2 膜５及びSiO 2 膜層20a,b をトンネリングし、各SiN膜層18a,b,cに捕獲され情報が 記憶される。情報消去時は書込時と反対方向の電界を印 加し捕獲電子をチャンネル領域に戻してやる。情報読出 しの場合はドレインとソース間に電圧を印加時チャネル 領域の電流の存否で判断する。 (57) [Summary] (Correction) [Purpose] A trap type with a wide memory window that can read accurately even when data is written at a low voltage of about 6V, and has a large memory window width and excellent charge retention performance. A nonvolatile semiconductor memory device is provided. [Structure] n + drain 26 and n + source 28 in p-type Si substrate 3 Forming the channel region 30. A SiO 2 thin film 5 is formed on the upper surface thereof, then a multilayer laminated insulating film 22 is formed, and a poly Si film 24 is formed on the upper surface thereof. The multilayer laminated insulating film 22 has a structure in which the SiN film layers 18 and the SiO 2 film layers 20 are alternately laminated in the order of three layers. When an electric field is applied between the poly-Si film 24 and the channel region 30, The electrons in the channel region are affected by the SiO 2 film 5 and the SiO 2 film layers 20a and 20b. Are tunneled, and information is stored by being captured in each SiN film layer 18a, 18b, 18c. At the time of erasing information, an electric field in the opposite direction to that at the time of writing is applied to return trapped electrons to the channel region. In the case of reading information, when a voltage is applied between the drain and the source, it is determined by the presence or absence of the current in the channel region.

Inventors

• 👤 Noriyuki Shimoji
• 👤 規之 下地
• 👤 Takanori Ozawa
• 👤 孝典 小澤
• 👤 Hironobu Nakao
• 👤 広宣 中尾

Bibliographic Details