← Back to Patent Explorer
JPH0456513A Expired / Lapsed JP ⏱️ 0.0 years remaining

Logic circuit

Assignee: Panasonic Holdings Corp
•
Filing: 1990-06-26
•
Granted: —
•
Expires: 2010-06-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To make the circuit operation stable by feeding back an inphase signal being a delayed output signal to an input 1st stage transistor(TR) to control an input switching level. CONSTITUTION:The circuit is provided with a circuit block PL comprising P-channel MOS TRs Qpl1, Qpl2 and a circuit block PN comprising N-channel MOS TRs Qnl1, Qnl2. Moreover, a 1st P-channel MOS TR Qpl receiving a signal in phase with an output signal O as its gate input and a 2nd P-channel MOS TR Qp2 receiving a ground voltage VSS as its gate input are connected in parallel between the circuit block PL and a power supply VCC. In such a case, since the TR QP1 acts like a current control TR, not only an output signal is settled quickly but also a current flowing between power supplies is less when at least one of input signals 11,12 transfers to a logic voltage H. Thus, the entire circuit is operated stably.

Inventors

  • 👤 Hiroshige Hirano
  • 👤 博茂 平野

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 00:07
CPC Classifications
—

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

JPS5648725A Cited
JPS59212028A Cited
JPH03175728A Cited

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag