Semiconductor integrated circuit device

Abstract

Abstract PURPOSE:To form a resistive element and a capacitive element without lessening a gate in scale to obtain a chip where analogs are mixedly provided in a gate array of gate structure in which chips are arranged on a logic gate. CONSTITUTION:A MOS transistor provided closely covering all the surface is formed on a thin silicon section on an insulating layer 15, and the arranged logic gates are formed in an element structure of SOI. A capacitor lower electrode 12, a dielectric film 13, and a capacitor upper electrode 14 used for analogization and a resistive element are formed under the insulating layer 15 as buried in the insulating film 11 on the substrate 10 or an insulating substrate, and the capacitor and the resistor concerned are led out to the surface of a chip through the intermediary of a contact hole 23 provided to the insulating layer 15. As a polishing stopper 16 is formed on the insulating layer 15, a silicon section thin in SOI structure is obtained by polishing a substrate.

Inventors

• 👤 Akihiko Ochiai
• 👤 落合　昭彦

Bibliographic Details