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JPH0342873A Expired / Lapsed JP ⏱️ 0.0 years remaining

semiconductor equipment

Assignee: Seiko Epson Corp
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Filing: 1989-07-11
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Granted: —
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Expires: 2009-07-11
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Abstract

Abstract PURPOSE:To reduce the areas of source/drain regions and to highly integrate a semiconductor device by forming a second groove in the bottom of a first groove formed on a substrate, forming source/drain on the side faces of both the grooves, and forming a gate electrode on the bottom of the first groove through a PSG film. CONSTITUTION:A silicon substrate 101 is etched to form first and second grooves, a silicon oxide film 108 is formed by thermally oxidizing, and a threshold voltage is regulated by B ion implanting. Then, after a polycrystalline silicon film is deposited, As ions are implanted. Thereafter, after a ramp annealing is conducted in a nitrogen atmosphere, the polycrystalline silicon is dry etched except a gate electrode 104. Then, As ions are implanted under predetermined conditions, and source/drain 102, 103 are formed. Subsequently, after a PSG film is formed as an interlayer insulating film 106, it is isotropically etched, and the side faces of the first groove are opened. After aluminum is sputtered, aluminum wirings 105 are patterned, a passivation 107 of a silicon oxide film is eventually deposited to obtain a MOSFET structure.

Inventors

  • 👤 Yutaka Maruo
  • 👤 丸尾 豊

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-28 18:51
CPC Classifications
—

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