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JPH0341523A Expired / Lapsed JP ⏱️ 0.0 years remaining

Parallel process ordering system

Assignee: NTT Inc
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Filing: 1989-07-10
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Granted: —
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Expires: 2009-07-10
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Abstract

Abstract PURPOSE:To attain parallel execution in parallel process ordering by providing respective network switches constituting a multistage connection network with a function for connecting instructions. CONSTITUTION:Respective processors PEi 1 are connected so as to directly access respective memory modules MMi 2, but are connected through the multistage connection network MIN 3 at the time of accessing the memory module MMj (j not equal to i) and communicating with a processor PEj. Namely, the subject system has a mechanism for connecting a swap-and-send instruction (SAS instruction) and plural SAS instructions meating in the MIN 3. Thus, ordering can be attained by connecting a communication channel between parallel processing and the parallel execution of ordering can be attained.

Inventors

  • 👤 Masaru Takesue
  • 👤 武末 勝

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 19:37
CPC Classifications
—

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