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JPH0335523A Expired / Lapsed JP ⏱️ 0.0 years remaining

Method of forming wiring of semiconductor device

Assignee: Fujitsu Ltd
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Filing: 1989-07-01
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Granted: —
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Expires: 2009-07-01
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Abstract

Abstract PURPOSE:To form a multilayer structure wiring which does not become an uneven state even if a boundary between a silicide layer and a polysilicon layer is heat treated by forming an impurity containing glass layer under the polysilicon layer, forming the polysilicon lower layer in an amorphous state, crystallizing to anneal it, and annealing for diffusion of impurity from the impurity containing glass layer. CONSTITUTION:An SiO2 layer 12 is formed on a silicon single crystalline substrate 11 by a normal CVD method. Then, a PSG layer 13 is formed on the layer 12 by a normal CVD method, and a silicide layer 15 is formed on the layer 14 by a sputtering method. Then, an SiO2 layer 16 is formed on the layer 15 by a normal CVD method, and the formed layer 15 is annealed to be crystallized from an amorphous state. In this case, when it is heat treated in an N2 atmosphere, the SiO2 layer is provided on the metal layer. Thus, the multilayer structure wiring formed in this manner is substantially flat in the boundary between the silicide and the polysilicon, and an even part which is heretofore problem is reduced.

Inventors

  • 👤 Takae Sasaki
  • 👤 佐々木 孝江

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 03:49
CPC Classifications
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