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JPH0334569A Expired / Lapsed JP ⏱️ 0.0 years remaining

Static type semiconductor storage device

Assignee: Toshiba Corp
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Filing: 1989-06-30
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Granted: —
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Expires: 2009-06-30
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Abstract

Abstract PURPOSE:Not only to ease the pattern layout but also to take the ratio of length to width of the gate of an FET large enough by complimentarily forming a pair of P-channel MOS transistors of the conductive film at the second layer and the conductive layer at the third layer. CONSTITUTION:By the polysilicon film at the third layer which is formed through a thin gate insulating film 16 on a polysilicon film at the second layer, the source region SP2, the channel region CP2, and the drain region DP2 of a second P-channel MOS transistor P2 are formed. The gate electrode GP1 of a first P-channel MOS transistor P1 is so formed as to range from this drain region DP2. By the polysilicon film at the fourth layer, which is formed through an insulating film 18 on the polysilicon film at the third layer, VSS wiring 19 in contact with the source region SN1 of a driving transistor N1 is formed.

Inventors

  • 👤 Takayuki Otani
  • 👤 大谷 孝之

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 20:15
CPC Classifications
—

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