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Patent JPH03230573A successfully refreshed from Google Patents.
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JPH03230573A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device and manufacture thereof

Assignee: Panasonic Holdings Corp
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Filing: 1990-02-05
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Granted: —
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Expires: 2010-02-05
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Abstract

Abstract PURPOSE:To allow a semiconductor device to have a good contact resistance by forming Ti/TiN films to the electrode contact window of an n-type impurity diffusion layer and a contact having no barrier metal to the electrode contact widow of a p-type impurity diffusion layer. CONSTITUTION:After electrode contact windows 201, 203, 204, and 205 are formed by etching, a Ti and TiN films 10 and 11 which are the first and second coatings, respectively, are successively formed as barrier metals on the entire surface of a wafer. Then a resist pattern is formed and the source-drain electrode contact widow 202 and P well layer electrode contact window 206 of a PMOS transistor are formed by etching an SiO2 film 9 containing B and P and the Ti and TiN films 10 and 11. Accordingly, the Ti/TiN films can be formed to the contacts of an n<+> layer 7 and gate electrode 6 which has an n-type high concentration as barrier metals and a contact having no barrier metals of the Ti/TiN film can be formed on a p<+> layer 8. Therefore, effective contacts can be formed.

Inventors

  • 👤 Akio Miyajima
  • 👤 明夫 宮島
  • 👤 Shohei Shinohara
  • 👤 篠原 昭平

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 04:46
CPC Classifications
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