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JPH03225946A Expired / Lapsed JP ⏱️ 0.0 years remaining

Package for semiconductor device use

Assignee: NEC Corp
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Filing: 1990-01-31
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Granted: —
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Expires: 2010-01-31
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Abstract

Abstract PURPOSE:To increase a heat-dissipating efficiency and to reduce a mounting height by providing the following: a plurality of leads, for electrical connection use, which are extracted from edge parts, excluding a semiconductor-chip mounting region, on one face of a ceramic substrate and which are arranged at prescribed intervals; and a plurality of leads, for heat-dissipating use, which extend from the chip mounting region part and which are arranged at narrow intervals. CONSTITUTION:Leads 4 for electrical connection use are arranged at a prescribed pitch in a lattice shape at edge parts on the rear surface of a ceramic substrate 1. The leads 4 for electrical connection use are connected electrically to connecting terminals. The central part on the rear surface of the ceramic substrate 1 is used as a heat-dissipating region 7; leads 3 for heat-dissipating use are arranged in the heat-dissipating region 7; their diameter is formed to be thin at 2/3 of the diameter of the leads 4 for electrical connection use. The leads 3 for heat-dissipating use are bonded to the ceramic substrate 1 by using a brazing material such as Au, Cu or the like. A semiconductor chip 2 is fixed and bonded inside a second recessed part of the ceramic substrate 1 in such a way that its electrode formation face is faced upward. Electrodes of the semiconductor chip 2 are connected to the connecting terminals by bonding wires 6.

Inventors

  • 👤 Hiroyuki Uchida
  • 👤 浩享 内田

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 21:52
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/03; H05K1/0306

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