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JPH03219650A Expired / Lapsed JP ⏱️ 0.0 years remaining

Probe card

Assignee: Takeda Sangyo Co Ltd
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Filing: 1990-01-24
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Granted: —
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Expires: 2010-01-24
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Abstract

Abstract PURPOSE:To make a probe card itself sharply small-sized and to surely realize high-density multi-pin structure by a method wherein a group of bumps and an electricity-transmitting route are formed on a silicon substrate. CONSTITUTION:A taper part 2 is formed in the peripheral edge part of a single- crystal silicon substrate 1; the substrate is doped with p-type impurities. A group of bumps 3 which are designed so as to be situated on pad positions of a wafer chip are formed in the pad positions by an etching method. Then, in order to lower a resistance value, acceptor impurities whose valence is +3 or donor impurities whose valence is +5 are introduced into the bumps 3 formed by an etching operation. Since the p-type silicon substrate 1 is used in this case, n-type impurities whose valence is +5 are implanted into the group of bumps 3. Interconnection patterns on the silicon substrate 1 on which metal electricity-transmitting routes 5 have been vapor-deposited are formed from the group of bumps 3 up to the taper part 2 on the silicon substrate 1. In addition, compensation circuits as countermeasures for high-frequency noise are wired to the metal electricity-transmitting routes 5.

Inventors

  • 👤 Kenjiro Bando
  • 👤 坂東 憲二郎
  • 👤 Hajime Tomokage
  • 👤 肇 友景

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 21:25
CPC Classifications
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