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JPH03218679A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Toshiba Corp
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Filing: 1990-01-24
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Granted: —
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Expires: 2010-01-24
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Abstract

Abstract PURPOSE:To enhance a channel in width per element planar area in a planar direction by a method wherein pillar-shaped regions are formed on a semiconductor substrate, and an FET provided with a gate electrode is formed on the side face of the pillar-like region. CONSTITUTION:Pillar-shaped regions 31-37 protrudent higher than the primary face of a substrate 1 are formed in rows on the element region of the substrate 1. A thermally oxidized film serving as a gate insulating film 4 is formed on the surface of the element region including the surfaces of the pillar-shaped regions 31-37, for instance, through a thermal oxidation method. Then, a polysilicon layer to serve as a gate electrode 5 is deposited on the whole face through a CVD method and etched as deep as its thickness through a RIE method of anisotropic etching to be left on the side face of the pillar-shaped regions 31-37 as the gate electrode 5. At this point, the formed electrode 5 covers all the pillar-shaped regions 31-37 and functions as a single gate electrode 5 in the element region. By this setup, a channel can be enhanced in width per element planar area in the widthwise direction of a FET, so that a semiconductor device of this design can be enhanced in a current drive capacity.

Inventors

  • 👤 Tomohisa Mizuno
  • 👤 智久 水野

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-29 22:38
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/63; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS6435957A Cited
JPH01293666A Cited
JPH01300566A Cited

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