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JPH03214232A Expired / Lapsed JP ⏱️ 0.0 years remaining

Floating point adder/subtractor

Assignee: NEC Corp
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Filing: 1990-01-18
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Granted: —
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Expires: 2010-01-18
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Abstract

Abstract PURPOSE:To perform the addition/subtraction with floating points at a high speed by calculating the updating of an exponent part which is carried out in a rounding state of a mantissa part before the execution of a rounding operation and outputting selectively the correct value of an exponent in accordance with the rounding result. CONSTITUTION:A 2nd updating device 120 adds '2' to the exponent part 103 of the larger one of two operands when an overflow occurs at the mantissa part at the time of the addition and in parallel with the processing of a 1st updating device 119. When a normalizing left shift is carried out at the mantissa part at the time of the subtraction, the value obtained by adding '1' to the left shift is subtracted from the part 103. When no overflow occurs at the mantissa part owing to a rounding operation, the output of the device 120 is selectively outputted via a selector 123. Meanwhile the output of the device 119 is selectively outputted via the selector 123 when no overflow occurs at the mantissa part. Thus, the addition/subtraction of the floating points can be performed at a high speed.

Inventors

  • 👤 Fuyuki Okamoto
  • 👤 冬樹 岡本

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 13:16
CPC Classifications
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