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JPH03210683A Expired / Lapsed JP ⏱️ 0.0 years remaining

Multiplier

Assignee: NEC Corp
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Filing: 1990-01-12
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Granted: —
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Expires: 2010-01-12
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Abstract

Abstract PURPOSE:To obtain a multiplier having the excellent linearity and a wide dynamic range by preparing the same circuit configuration to both 1st and 2nd input voltage and also the same multiplier characteristic to both input voltage respectively. CONSTITUTION:A 1st square circuit 8 contains a pair of unmatched differential amplifiers where the gates of transistors TR M55 - M58 are connected to each other with the input/output operations set adverse to each other and input pairs having the TR sizes different from each other. Then the circuit 8 squares the output V1+V2 of an adder 6. A 2nd square circuit 9 contains a pair of unmatched differential amplifiers where the gates of the TR M63 - M66 are connected to each other with the input/output operations set adverse to each other and input pairs having the TR sizes different from each other. Then the circuit 9 squares the output V1 - V2 of a 1st subtractor 7. A 2nd subtractor 10 secures the difference between both circuits 8 and 9 and obtains the multiplication outputs 4V1 and V2 proportional to the product of the 1st input voltage V1 and the 2nd input voltage V2. In such configuration, the excellent linearity is ensured for a multiplier.

Inventors

  • 👤 Katsuharu Kimura
  • 👤 克治 木村

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 18:53
CPC Classifications
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